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HT47C10L
R-F Type Low Voltage 8-Bit Mask MCU
Technical Document
* Tools Information * FAQs * Application Note -
HA0029E HA0030E HA0034E HA0036E HA0045E
Using the Time Base Function in the HT47R20A-1 Using the RTC in the HT47R20A-1 Using the Buzzer Function in the HT47R20A-1 Using the PFD Function in the HT47R20A-1 Distinguishing between the Different Devices in the HT47 MCU Series
Features
* Operating voltage: 1.2V~2.2V * Eight bidirectional I/O lines * On-chip 32kHz/128kHz built-in RC oscillator * HALT function and wake-up feature reduce power
consumption
* One LCD driver with 94 segments, 1/4 duty, 1/2 bias * RC type A/D converter * Two-level subroutine nesting * Bit manipulation instruction * 16-bit table read instruction * Up to 122ms instruction cycle with 32768Hz system
(Mask option; 128kHz is selected especially for EL driving)
* Watchdog Timer * 1K16 program memory ROM * 328 data memory RAM * One time base (TB) * One buzzer output * One EL output * One externally adjustable low voltage detector
clock
* All instructions in one or two machine cycles * 63 powerful instructions * 44-pin QFP package
General Description
The HT47C10L is an 8-bit high performance RISC-like microcontroller. Its single cycle instruction and two-stage pipeline architecture make it suitable for high speed applications. The device is suited for clinical thermometers.
Rev. 1.90
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November 30, 2005
HT47C10L
Block Diagram
S y s te m In te rru p t C ir c u it STACK1 STACK0 TM 1 TM 0 TE IN T C T im e r A A /D In s tr u c tio n R e g is te r C lo c k RC Type A /D C o n v e rte r R C IN RREF RSEN P u ls e W id th M e a s u re m e n t M o d e C o n tro l TM 1 TM 0 TON C lo c k ( fS
YS
)
P ro g ra m ROM
P ro g ra m C o u n te r
MP
M U
X
DATA M e m o ry
T im e r B
T im e B a s e W DT In s tr u c tio n D ecoder ALU S h ifte r PA 1 2 8 k H z /3 2 k H z R C O s c illa to r * M a s k O p tio n BP ACC LCD M e m o ry C1 C2 D o u b le V o lta g e L C D D r iv e r LVD VDD VSS RES TEST1 TEST2 MUX L C D B Z /B Z E L 1 /E L 2 STATUS P o rt A PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 LVD /B Z /B Z /E L 1 /E L 2 fS
YS
=32kH z
T im in g G e n e ra to r fS Y S = 3 2 k H z
VCC
C O M 0~C O M 3
SEG 0~SEG 8
Pin Assignment
V TES TES R NC LVD 0 /B Z 1 /B Z /E L 1 /E L 2 PA4 PA5 PA6 PA7 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
NC VCC C2 C1 NC NC NC DD T1 T2 ES
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
PA PA2 PA3
PA
H T47C 10L 4 4 Q F P -A
NC SE SE SE SE SE SE SE SE SE CO
G0 G1 G2 G3 G4 G5 G6 G7 G8 M3
CO CO CO NC NC NC RR RS RC VS NC S EF EN IN M0 M1 M2
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HT47C10L
Pin Description
Pin Name RES I/O I Schmitt trigger reset input. Active low Bidirectional 2-bit input/output port. Each bit can be a wake-up input. The PA0 and PA1 are pin-shared with the BZ and BZ, respectively. Once the PA0 and PA1 are selected as buzzer driving outputs, the output signals come from an internal buzzer clock generator. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor Function
PA0/BZ PA1/BZ
I/O I/O
PA2/EL1 PA3/EL2
Bidirectional 2-bit input/output port. Each bit can be a wake-up input. The PA2 and PA3 are pin-shared with the EL1 and EL2, respectively. Once the PA2 and PA3 are selected as I/O EL driving outputs, the output signals come from an internal EL clock generator. I/O Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor I/O 3/4 Bidirectional 4-bit input/output port. Each bit can be a wake-up input. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor Negative power supply, ground For double voltage. VCC=2VDD VCC: LCD power supply voltage, a capacitor has to be connected between VCC and VSS. C1, C2: Switching pins for VCC, a capacitor has to be connected between C1 and C2 LCD driver outputs for LCD panel segments and commons. Positive power supply Low voltage detector. A resistor has to be connected between VSS and LVD RC type A/D converter input pin for RC oscillation. RC type A/D converter output pin for reference resistor oscillation. RC type A/D converter output pin for sensor resistor oscillation TEST mode input pin with pull-high resistor. Let open in normal mode TEST mode input pin. Let open in normal mode
PA4~PA7 VSS
VCC, C1, C2
3/4
SEG8~SEG0 COM3~COM0 VDD LVD RCIN RREF RSEN TEST1 TEST2 TRIM1~TRIM6
O 3/4 B I O O I I
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+2.5V Input Voltage..............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
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HT47C10L
D.C. Characteristics
Symbol VDD VCC VLVD Parameter Operating Voltage LCD Voltage Low Voltage Detector Voltage Test Conditions VDD 3/4 3/4 3/4 Conditions 3/4 VCC=2VDD *RLVD=30kW No load, fOSC=128kHz fSYS=32kHz, A/D Off, LVD disable No load, fOSC=128kHz fSYS=32kHz, A/D On, LVD disable *R=30kW, *C=2200pF No load, fOSC=32kHz fSYS=32kHz, A/D Off, LVD disable No load, fOSC=32kHz fSYS=32kHz, A/D On, LVD disable *R=30kW, *C=2200pF ILVD ISTB1 LVD Current Standby Current (LVD Disable, LCD Off) 1.5V LVD enable 1.5V No load, system HALT A/D Off, LVD Off No load, fOSC=128kHz fSYS=32kHz, A/D Off, LVD disable No load, fOSC=32kHz fSYS=32kHz, A/D Off, LVD disable 3/4 3/4 3/4 3/4 Min. 1.2 2.4 1.25 3/4 Typ. 1.5 3 1.3 9 Max. 2.2 4.4 1.35 20 Ta=25C Unit V V V mA
3/4
26
50
mA
IDD
Operating Current
1.5V
3/4
5
10
mA
3/4
23
40
mA
3/4 3/4 3/4
50 3/4
100 1
mA mA mA
7
15
ISTB2
Standby Current (LCD On)
1.5V
3/4 0 0.8VDD 0 0.9VDD 0.5
2.5 3/4 3/4 3/4 3/4 0.8
5 0.3VDD VDD 0.4VDD VDD 3/4
mA V V V V mA
VIL1 VIH1 VIL2 VIH2 IOL1
Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RES) Input High Voltage (RES) Sink Current PA0 (BZ), PA1 (BZ), PA2 (EL1), PA3 (EL2), PA4~PA7 Source Current PA0 (BZ), PA1 (BZ), PA2 (EL1), PA3 (EL2), PA4~PA7 Common Output Sink Current
3/4 3/4 3/4 3/4
1.5V VOL=0.15V
IOH1 IOL2 IOH2 IOL3 IOH3 RPH1 RPH2 Note:
1.5V VOH=1.35V 1.5V VOL=0.3V (1/2 bias)
-0.3 50 -50 50 -50 75 75
-0.6 100 -100 100 -100 150 150
3/4 3/4 3/4 3/4 3/4 300 300
mA mA mA mA mA kW kW
Common Output Source Current 1.5V VOH=2.7V (1/2 bias) Segment Output Sink Current 1.5V VOL=0.3V (1/2 bias)
Segment Output Source Current 1.5V VOH=2.7V(1/2 bias) Pull-high Resistance of I/O Ports 1.5V VIL=0V Pull-high Resistance of TEST 1.5V VIL=0V
*R means the resistance of RC type A/D converter *C means the capacitance of RC type A/D converter *RLVD value may be different for different lot
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HT47C10L
A.C. Characteristics
Symbol f32K f128K tRES fAD Parameter Oscillator Clock (32kHz option) Test Conditions VDD 1.5V Conditions 3/4 3/4 3/4 3/4 Min. 26 102 100 3/4 Typ. 32 128 3/4 3/4 Max. 40 160 3/4 50 Ta=25C Unit kHz kHz ms kHz
Oscillator Clock (128kHz option) 1.5V External Reset Low Pulse Width 1.5V A/D Converter Frequency 1.5V
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HT47C10L
Functional Description
Execution Flow The HT47C10L system clock is derived from an about 32kHz built-in RC oscillator. The system clock is internally divided into four non-overlapping clocks (T1, T2, T3 and T4). One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in one cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The 10-bit program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a maximum of 1024 addresses. After accessing a program memory word to fetch an inT1 T2 T3 T4 T1 T2
struction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required.
T3 T4 T1 T2 T3 T4
S y s te m
C lo c k
In s tr u c tio n C lo c k
PC
PC
PC+1
PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Program Counter *9 0 0 0 *9 #9 S9 *8 0 0 0 *8 #8 S8 *7 0 0 0 @7 #7 S7 *6 0 0 0 @6 #6 S6 *5 0 0 0 @5 #5 S5 *4 0 0 0 @4 #4 S4 *3 0 0 1 @3 #3 S3 *2 0 1 0 @2 #2 S2 *1 0 0 0 @1 #1 S1 *0 0 0 0 @0 #0 S0
Mode Initial Reset Timer/event Counter Interrupt Time Base Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine
Program Counter+2
Program Counter Note: *9~*0: Program counter bits S9~S0: Stack register bits #9~#0: Instruction code bits @7~@0: PCL bits
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HT47C10L
Program Memory - ROM The program memory is used to store the program instructions, which are to be executed. It also contains data, table, and interrupt entries, and is organized into 102416 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage:
* Location 000H
000H 004H 008H
00CH 010H P ro g ra m ROM D e v ic e In itia liz a tio n P r o g r a m T im e r /e v e n t C o u n te r In te r r u p t S u b r o u tin e T im e B a s e In te r r u p t S u b r o u tin e
This area is reserved for the initialization program. After chip reset, the program always begins execution at location 000H.
* Location 004H
n00H nFFH
L o o k - u p T a b le ( 2 5 6 w o r d s )
This area is reserved for the timer/event counter interrupt service program. If timer interrupt results from a timer/event counter A or B overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 004H.
* Location 008H
3FFH
L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 6 b its
N o te : n ra n g e s fro m
0 to 3
Program Memory tine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions need two cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. Stack Register - STACK This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is organized into two levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow alTable Location
This area is reserved for the time base interrupt service program. If a time base interrupt occurs, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
* Table location
Any location in the ROM space can be used as look-up tables. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the higher-order byte of the table word are transferred to the TBLH. The table higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (interrupt service routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main rouInstruction(s) TABRDC [m] TABRDL [m]
*9 P9 1
*8 P8 1
*7 @7 @7
*6 @6 @6
*5 @5 @5
*4 @4 @4
*3 @3 @3
*2 @2 @2
*1 @1 @1
*0 @0 @0
Table Location Note: *9~*0: Bits of table location P9~P8: Bits of current program counter Rev. 1.90 7 November 30, 2005 @7~@0: Bits of table pointer
HT47C10L
lowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent two return addresses is stored). Data Memory - RAM The data memory is designed with 548 bits. The data memory is divided into two functional groups: special function registers and general-purpose data memory (328). Most are read/write, but some are read only.
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27 28 5F 60 H H H H TM RAH TM RAL TM RC TM RBH TM RBL ADCR OPT1 OPT2 G e n e r a l- P u r p o s e D a ta M e m o ry (3 2 B y te s ) PA PAC S p e c ia l P u r p o s e D a ta M e m o ry In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH TBC STATUS IN T C
The special function registers include the indirect addressing register 0 (00H), the memory pointer register 0 (MP0; 01H), the indirect addressing register 1 (02H), the memory pointer register 1 (MP1;03H), the bank pointer (BP;04H), the accumulator (ACC;05H), the program counter lower-order byte register (PCL;06H), the table pointer (TBLP;07H), the table higher-order byte register (TBLH;08H), the time base control register (TBC;09H), the status register (STATUS;0AH), the interrupt control register 0 (INTC;0BH), the I/O registers (PA;12H), I/O port control register (PAC;13H), the timer/event counter A higher-order byte register (TMRAH; 20H), the timer/event counter A lower-order byte register (TMRAL; 21H), the timer/event counter control register (TMRC; 22H), the timer/event counter B higher-order byte register (TMRBH; 23H), the timer/event counter B lower-order byte register (TMRBL; 24H), the RC oscillator type A/D converter control register (ADCR; 25H) and the option register (OPT1; 26H, OPT2; 27H). The remaining space before the 60H are reserved for future expanded usage and reading these location will return the result 00H. The general-purpose data memory, addressed from 60H to 7FH, is used for data and control information under instruction command. All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations. Except for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i instruction, respectively. They are also indirectly accessible through memory pointer registers (MP0;01H, MP1;03H). Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] access data memory pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly will return the result 00H. Writing indirectly results in no operation. The function of data movement between two indirect addressing registers are not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers which can be used to access the data memory by combining corresponding indirect addressing registers. MP0 only can be applied to data memory, while MP1 can be applied to data memory and LCD display memory. Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and is capable of carrying out immediate data operations. The data movement between two data memory locations must pass through the accumulator.
:U nused
R e a d a s "0 0 "
7FH
RAM Mapping (Bank 0)
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HT47C10L
Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
Interrupts The HT47C10L provides an internal timer/event counter interrupt and an internal time base interrupt. The interrupt control register (INTC;0BH) contains the interrupt control bits to set the enable/disable and interrupt request flags. Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval, but only the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the programmer may set the EMI bit and the corresponding bit of INTC allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified locations in the program memory. Only the program counter is pushed onto the stack. If the contents of the register and status register (STATUS) is altered by the interrupt service program which corrupts the desired control sequence, the contents must be saved first. The internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (TF; bit 4 of INTC), caused by a timer A or timer B overflow. When the interrupt is enabled, and the stack is not full and the TF bit is set, a subroutine call to location 04H will occur. The related interrupt request flag (TF) will be reset and the EMI bit cleared to disable further interrupts.
The ALU not only saves the results of a data operation but can change the status register. Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF) and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flags. In addition it should be noted that operations related to the status register may give different results from those intended. The TO and PDF flags can only be changed by the watchdog timer overflow, system power-up, clearing the watchdog timer and executing the HALT instruction. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly.
Bit No. 0
Label C
Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by either a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Unused bit, read as 0 STATUS (0AH) Register
1 2 3 4 5 6 7
AC Z OV PDF TO 3/4 3/4
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HT47C10L
Bit No. 0 1 2 3 4 5 6 7 Label EMI ETI ETBI 3/4 TF TBF 3/4 3/4 Function Control the master or global interrupt (1=enabled; 0=disabled) Control the timer/event counter interrupt (1=enabled; 0=disabled) Control the time base interrupt (1=enabled; 0=disabled) Unused bit, read as 0 Timer/event counter interrupt request flag (1=active; 0=inactive) Time base interrupt request flag (1=active; 0=inactive) Unused bit, read as 0 Unused bit, read as 0 INTC (0BH) Register Watchdog Timer - WDT The clock source of the WDT (fS) is fSYS. The timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The Watchdog timer can be disabled by software option. If the Watchdog timer is disabled, all the executions related to the WDT result in no operation. The HALT instruction is executed, WDT still counts if fOSC is on and can wake-up from HALT mode due to the WDT time-out. The WDT overflow under normal operation will initialize chip reset and set the status bit TO. Whereas in the HALT mode, the overflow will initialize a warm reset only the Program Counter and SP are reset to zero. To clear the contents of WDT, three methods are adopted, external reset (a low level to RES), software instruction, or a HALT instruction. The software instruction is CLR WDT. Any execution of the CLR WDT instruction will clear the WDT. The WDT may reset the chip because of the time-out. The WDT time-out period ranges from fS/215~fS/216. The CLR WDT instruction only clear the last two-stage of the WDT. Multi-function Timer The HT47C10L provides a multi-function timer for the WDT and time base but with different time-out periods. The multi-function timer consists of an 8-stage divider and a 7-bit prescaler, with the clock source coming from fSYS. The multi-function timer also provides a fixed frequency signal (fS/8) for the LCD driver circuits, and buzzer output.
fS /2 7 - b it P r e s c a le r
15
The time base interrupt is initialized by setting the time base interrupt request flag (TBF; bit 5 of INTC), caused by a regular time base signal. When the interrupt is enabled, and the stack is not full and the TBF bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (TBF) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET does not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. No. a b Interrupt Source Timer/event counter interrupt Time base interrupt Priority Vector 1 2 04H 08H
Oscillator Configuration The HT47C10L provides one built-in RC oscillator which frequency (fOSC) is 32kHz or 128kHz decided by mask option. However, the CPU system clock (fSYS) is always 32kHz. The HALT mode may stop the oscillator decided by software option. User should select 128kHz mask option for EL driving mode.
fS /2 8 - s ta g e D iv id e r LCD D r iv e r fS /8 B u z z e r fS /4 ~ fS /3 2
8
fS
YS
=32768Hz
fS
TFF R
fS /2
16
TFF R
T im e - o u t R e s e t 15 16 fS /2 ~ fS /2 W D T C le a r
8 to 1 M u x . T im e B a s e O u t
RT0~RT2
Multi-function Timer
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Time Base - TB The time base is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to fS/215 by software programming. Writing data to RT2, RT1 and RT0 (bits 2, 1, 0 of TBC;09H) yields various time-out periods. If a time base time-out occurs, the related interrupt request flag (TBF; bit 5 of INTC) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 08H occurs. When the HALT instruction is executed, the time base still works and can wake-up from HALT mode if fOSC is on. If the TBF is set 1 before entering the HALT mode, the wake-up function will be disabled. RT2 0 0 0 0 1 1 1 1 RT1 0 0 1 1 0 0 1 1 RT0 0 1 0 1 0 1 0 1 Time Base Divided Factor 28 29 210 211 212 213 214 215 If an interrupt request flag is set to 1 before entering the HALT mode the wake-up function of the related interrupt will be disabled. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by more than one cycle. However, if the wake-up results in the next instruction execution, the execution will be performed immediately. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT mode. Reset There are three ways in which a reset may occur.
* RES reset during normal operation * RES reset during HALT mode * WDT time-out reset during normal operation
Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following.
* The fOSC and fSYS will still work or stop depend on
The WDT time-out during HALT mode is different from other chip reset conditions, since it can perform a warm reset that just resets the Program Counter and SP leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions System power-up RES reset or LVR reset during normal operation RES reset or LVR reset wake-up from HALT mode WDT time-out during normal operation WDT wake-up from HALT mode
STANDBY option (Option register bit 5), but T1 will turn off. * The contents of the on-chip RAM and registers remain unchanged.
* The WDT will be cleared and recount again. * All I/O ports maintain their original status. * The PDF flag is set and the TO flag is cleared. * LCD driver can be off or on depend on STANDBY op-
Note: u means unchanged The chip-reset status of the functional units are shown below. Program Counter Interrupt Prescaler, Divider WDT, Time Base Timer/event Counter Input/output Ports Stack Pointer 000H Disabled Cleared Clear. After master reset, begin counting Off Input mode Points to the top of the stack
tion (Option register bit 5)
* The time base will stop or run depends on STANDBY
option (Option register bit 5). The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If awakening from an interrupt, two sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, a regular interrupt response takes place.
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HT47C10L
HALT W DT
RES
W a rm
R eset
W DT T im e - o u t R eset
E x te rn a l C o ld R eset
V
DD
VDD RES RES S S T T im e - o u t C h ip R eset tS
ST
fS
YS
SST 1 0 - b it R ip p le C o u n te r P o w e r - o n D e te c tio n R e s e t C o n fig u r a tio n
R e s e t C ir c u it
R e s e t T im in g
Reset
The states of the registers are summarized in the following table: Register TMRAH TMRAL TMRC TMRBH TMRBL ADCR Program Counter MP0 MP1 ACC TBLP TBLH STATUS INTC TBC PA PAC OPT1 OPT2 Note: Reset (Power On) xxxx xxxx xxxx xxxx -000 1--xxxx xxxx xxxx xxxx ---x 0000 000H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx --00 xxxx --00 -000 ---- -111 1111 1111 1111 1111 --00 0010 0000 0000 WDT time-out (Normal Operation) xxxx xxxx xxxx xxxx -000 1--xxxx xxxx xxxx xxxx ---x 0000 000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --1u uuuu --00 -000 ---- -111 1111 1111 1111 1111 --00 0010 0000 0000 RES reset (Normal Operation) xxxx xxxx xxxx xxxx -000 1--xxxx xxxx xxxx xxxx ---x 0000 000H uuuu uuuu uuuu uuuu uuuu uuuu uuu uuuu uuuu uuuu --uu uuuu --00 -000 ---- -111 1111 1111 1111 1111 --00 0010 0000 0000 RES reset (HALT) xxxx xxxx xxxx xxxx -000 1--xxxx xxxx xxxx xxxx ---x 0000 000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --01 uuuu --00 -000 ---- -111 1111 1111 1111 1111 --00 0010 0000 0000 WDT time-out (HALT) uuuu uuuu uuuu uuuu -uuu u--uuuu uuuu uuuu uuuu ---u uuuu 000H* uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu --uu -uuu ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
* refers to warm reset u means unchanged x means unknown
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HT47C10L
Timer/Event Counter One 16-bit timer/event counter or RC type A/D converter is implemented in the HT47C10L. The ADC/TM bit (bit 1 of ADCR register) decides whether timer A and timer B are composed of one 16-bit timer/event counter or timer A and timer B are composed of RC type A/D converter. The TMRAL, TMRAH, TMRBL, TMRBH composed of one 16-bit timer/event counter, when ADC/TM bit is 0. The TMRBL and TMRBH are timer/event counter preload registers for lower-order byte and higher-order byte respectively. The timer/event counter clock source comes from system clock (fSYS) or external source (A/D clock from pad:RCIN). The external clock input allows the user to count external events, count external RC type A/D clock, measure time intervals or pulse widths, or generate an accurate time base. There are six registers related to the timer/event counter operating mode. TMRAH ([20H]), TMRAL ([21H]), TMRC ([22H]), TMRBH ([23H]), TMRBL ([24H]) and ADCR ([25H]). Writing to TMRBL only writes the data into a low byte buffer, and writing to TMRBH will write the data and the contents of the low byte buffer into the time/event counter preload register (16-bit) simultaneously. The timer/event counter preload register is changed by writing to TMRBH operations and writing to TMRBL will keep the timer/event counter preload register unchanged. Reading TMRAH will also latch the TMRAL into the low byte buffer to avoid the false timing problem. Reading TMRAL returns the contents of the low byte buffer. In other words, the low byte of the timer/event counter can not be read directly. It must read the TMRAH first to make the low byte contents of timer/event counter be latched into the buffer.
S y s te m C lo c k ( fS
YS
The TMRC is the timer/event counter control register, which defines the timer/event counter options. The timer/event counter control register define the operating mode, counting enable or disable and active edge. Writing to timer B location puts the starting value in the timer/event counter preload register, while reading timer A yields the contents of the timer/event counter. Timer B is timer/event counter preload register. The TM0 and TM1 bits define the operation mode. The event count mode is used to count external events, which means that the clock source (A/D clock) comes from an external (RCIN) pin. The timer mode functions as a normal timer with the clock source coming from the internal clock source (fSYS). Finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (A/D clock from pad:RCIN). The counting is based on the system clock (fSYS). In the event count, A/D clock or internal timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter (TMRAH and TMRAL) to FFFFH. Once overflow occurs, the counter is reloaded from the timer/event counter preload register (TMRBH and TMRBL) and generates the corresponding interrupt request flag (TF; bit 4 of INTC) at the same time. In the pulse width measurement mode with the TON and TE bits equal to one, once the RCIN has received a transient from low to high (or high to low if the TE bit is 0) it will start counting until the A/D Clock returns to the original level and resets the TON. The measured result will remain in the timer/event counter even if the activated transient occurs again. In other words, only one cycle measurement can be done. Until setting the TON,
) A D C /T M = 0
TM 1 TM 0 TE TM 1 TM 0 TON P u ls e W id th M e a s u re m e n t M o d e C o n tro l
D a ta B u s T im e r /e v e n t c o u n te r ( 1 6 b it T im e r A ) O v e r flo w
TM 0 A D C /T M
TON (A D C R
ADEN B it- 2 ) M o d e
R
to F c o n v e rte r
ADEN MODE RREF RSEN C o n tro l 20kW ~60kW R C IN A /D C lo c k
T im e r /e v e n t c o u n te r P r e lo a d R e g is te r ( 1 6 b it T im e r B )
R e lo a d
30kW
2200pF
Timer/Event Counter
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HT47C10L
the cycle measurement will function again as long as it receives further transient pulse. Note that in this operation mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of counter overflow, the counter is reloaded from the timer/event counter preload register and issues interrupt request just like the other two modes. To enable the counting operation, the timer on bit (TON; bit 4 of TMRC) should be set to 1. In the pulse width measurement mode, the TON will automatically be cleared after the measurement cycle is completed. But in the other two modes, the TON can only be reset by instructions. In the case of timer/event counter Off condition, writing Bit No. 0~2 3 4 Label 3/4 TE TON Unused bit, read as 0 To define the TMR active edge of timer/event counter (0= active on low to high; 1= active on high to low) To enable/disable timer counting (0= disabled; 1= enabled) To define the operating mode (TM1, TM0) 10= Timer mode (Internal clock: fSYS) 01= Event counter mode (External clock: A/D clock from pad RCIN) 11= Pulse width measurement mode (RCIN, fSYS) 00= Unused Unused bit, read as 0 TMRC (22H) Register data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter turns On, data written to the timer/event counter preload register is kept only in the timer/event counter preload register. The timer/event counter will still operate until overflow occurs. When the timer/event counter (reading TMRAH) is read, the clock will be blocked to avoid errors. As this may results in a counting error, this must be taken into consideration. It is strongly recommended to load first the desired value into TMRBL, TMRBH, TMRAL, and TMRAH registers then turn on the related timer/event counter for proper operation. Because the initial value of TMRBL, TMRBH, TMRAL and TMRAH are unknown. Function
5 6
TM0 TM1
7
3/4
Example for Timer/event counter mode (disable interrupt): clr tmrc clr adcr.1 clr intc.4 mov a, low (65536-1000) mov tmrbl, a mov a, high (65536-1000) mov tmrbh, a ; set timer mode ; clear timer/event counter interrupt request flag ; give timer initial value ; count 1000 time and then overflow
mov a, 01010000b mov tmrc, a
; timer clock source=fSYS and timer on
p10: clr wdt snz intc.4 jmp p10 clr intc.4 ; clear timer/event counter interrupt request flag ; program continue ; polling timer/event counter interrupt request flag
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RC Type A/D Converter RC type A/D converter is implemented in the HT47C10L. The A/D converter contains two 16-bit programmable count-up counters and the timer A clock source comes from the system clock (fSYS=32kHz). The timer B clock source comes from the external RC oscillator. The TMRAL, TMRAH, TMRBL, TMRBH are composed of the A/D converter when ADC/TM bit (bit 1 of ADCR register) is 1. The A/D converter timer B clock source may come from RREF~RCIN oscillation, RSEN~RCIN oscillation or RCIN external clock input. The timer A clock source is the system clock by setting (TM1, TM0=1, 0). There are six registers related to the A/D converter, i.e., TMRAH, TMRAL, TMRC, TMRBH, TMRBL and ADCR. The internal timer clock is input to TMRAH and TMRAL, the A/D clock is input to TMRBH and TMRBL. The OVB/OVA bit (bit 0 of ADCR register) decides whether timer A overflows or timer B overflows, then the TF bit is set and timer interrupt occurs. When the A/D converter mode timer A or timer B overflows, the TON bit is reset and stop counting. Writing TMRAH/TMRBH makes the starting value be placed in the timer A/timer B and reading TMRAH/TMRBH gets the contents of the timer A/timer B. Writing TMRAL/TMRBL only writes the data into a low byte buffer, and writing TMRAH/TMRBH will write the data and the contents of the low byte buffer into the timer A/timer B (16-bit) simultaneously. The timer A/timer B is changed by writing TMRAH/TMRBH operations and writing TMRAL/TMRBL will keep timer A/timer B unchanged. Reading TMRAH/TMRBH will also latch the TMRAL/TMRBL into the low byte buffer to avoid the false timing problem. Reading TMRAL/TMRBL returns the contents of the low byte buffer. In other word, the low byte of timer A/timer B can not be read directly. It must read the TMRAH/TMRBH first to make the low byte contents of timer A/timer B be latched into the buffer. The bit2 of ADCR decides which resistor and capacitor compose an oscillation circuit and input to TMRBH and TMRBL. The TM0 and TM1 bits of TMRC define the clock source of timer A. It is suggested that the clock source of timer A use the system clock. The TON bit (bit 4 of TMRC) is set 1 the timer A and timer B will start counting until timer A or timer B overflows, the timer/event counter generates the interrupt request flag (TF ; bit 4 of INTC) and the timer A and timer B stop counting and reset the TON bit to 0 at the same time. If the TON bit is 1, the TMRAH, TMRAL, TMRBH and TMRBL cannot be read or written to. Only when the timer/event counter is off and when the instruction MOV is used could those four registers be read or written to.
S y s te m
C lo c k ( fS TM 1 TM 0
YS
) A D C /T M = 1
TE TM 1 TM 0 TON R P u ls e W id th M e a s u re m e n t M o d e C o n tro l
D a ta B u s O V B /O V A = 0 T im e r A In te rru p t
TON TM 0 A D C /T M TON (A D C R ADEN B it- 2 ) M o d e to F c o n v e rte r T im e r B ADEN MODE RREF RSEN 30kW C o n tro l 20kW ~60kW R C IN /T M R A /D C lo c k D a ta B u s O V B /O V A = 1 R esetTO N
* A D E N is a c tiv e w h e n T O N = 1 in A /D m o d e fo r T im e r A & B ( A D C /T M = 1 ) o r w h e n T O N = 1 a n d c lo c k s o u r c e is A /D c lo c k in T M R m o d e fo r T im e r A & B ( A D C /T M = 0 ) * A D C /T M is b it 1 o f A D C R r e g is te r
CREF
2200pF
RC Type A/D Converter
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HT47C10L
Bit No. Label Function
0
In the RC type A/D converter mode, this bit is used to define the timer/event counter interrupt which comes from timer A overflow or timer B overflow. OVB/OVA (0= timer A overflow; 1= timer B overflow) In the timer/event counter mode, this bit is void. ADC/TM To define 16-bit timer/event counter or RC type A/D converter is enable. (0= timer/event counter enable; 1= A/D converter is enable) To define the A/D converter operating mode 0= RREF~CREF oscillation (reference resistor and reference capacitor) 1= RSEN~CREF oscillation (resistor sensor and reference capacitor) Low voltage detector disable/enable (0=disable; 1=enable) Low voltage flag (0=battery power good; 1=battery low) Unused bit, read as 0 ADCR (25H) Register
1
2 3 4 5~7
MODE BON BLF 3/4
Example for RC type AD converter mode (Timer A overflow): clr tmrc clr adcr.1 clr intc.4 mov a, low (65536-1000) mov tmrbl, a mov a, high (65536-1000) mov tmrbh, a ; set timer mode ; clear timers/event counter interrupt request flag ; give timer A initial value ; count 1000 time and then overflow
mov a, 00000010b mov adcr, a mov a, 00h mov tmrbl, a mov a, 00h mov tmrbh, a
; RREF~CREF; set RC type ADC mode; set Timer A overflow
; give timer B initial value
mov a, 01010000b mov tmrc, a
; timer A clock source=fSYS and timer on
p10: clr wdt snz intc.4 jmp p10 ; polling timer/event counter interrupt request flag
clr intc.4
; clear timer/event counter interrupt request flag ; program continue
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Example for RC type AD converter mode (Timer B overflow): clr tmrc clr adcr.1 clr intc.4 mov a, 00h mov tmrbl, a mov a, 00h mov tmrbh, a ; set timer mode ; clear timer/event counter interrupt request flag ; give timer A initial value
mov a, 00000011b mov adcr,a
; RREF~CREF; set RC type ADC mode; set Timer B overflow
mov a, low (65536-1000) mov tmrbl, a mov a, high (65536-1000) mov tmrbh, a
; give timer B initial value ; count 1000 time and then overflow
mov a, 00110000b mov tmrc, a
; timer A clock source=fSYS and timer on
p10: clr wdt snz intc.4 jmp p10 ; polling timer/event counter interrupt request flag
clr intc.4
; clear timer/event counter interrupt request flag ; program continue
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Input/Output Ports There is 8-bit bidirectional input/output port in the microcontroller, labeled PA which is mapped to the data memory of [12H]. All of these I/O lines can be used as input and output operations. For the input operation, these lines are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A, [m] (m=12H). For output operation, all the data is latched and remain unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with pull-high resistor structures can be reconfigured dynamically (i.e., on-the fly) under software control. To function as an input, the corresponding latch of the control register has to be set as 1. The pull-high resistor will be exhibited automatically. The input sources also depend on the control register. If the control register bit is 1, the input will read the pad state (mov and readmodify-write instructions). If the control register bit is 0, the contents of the latches will move to internal data bus (mov and read-modify-write instructions). The input paths (pad state or latches) of read-modify-write instructions are dependent on the control register bits. For output function, CMOS is the only configuration. This control register is mapped to locations 13H. After chip reset, these input/output lines stay at high levels (pull-high). Each bit of these input/output latches can be set or cleared by SET [m].i (m=12H) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CPLA [m], read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or to the accumulator. Each bit of the port A has the capability of waking-up the device. The PA0 and PA1 are pin-shared with BZ and BZ, respectively. If the BZ mode is selected, the output signal in output mode of PA0 (or PA1) will be BZ (or BZ) signal. The input mode always remains its original functions. The 4kHz buzzer output signals (in output mode) are controlled by the PA0 and PA1 data registers. The truth table of PA0/BZ and PA1/BZ are listed below. PA1 PA0 Data Register Data Register 0 (CLR PA.1) 1 (SET PA.1) X 0 (CLR PA.0) 0 (CLR PA.0) 1 (SET PA.0) PA1, PA0 Pad Function PA0=BZ, PA1=BZ PA0=BZ, PA1=0 PA0=0, PA1=0
OPTION Register: BZ Mode Enable The PA2 and PA3 are pin-shared with EL1 and EL2 signals, respectively. If the EL mode is selected, the output signal in output mode of PA2 (or PA3) will be the EL1 (or EL2) signal. The input mode always remains its original functions. The EL output signals (in output mode) are controlled by the PA2 data register only. The truth table of PA2/EL1 and PA3/EL2 are listed below. PA3 PA2 Data Register Data Register 0 or 1 0 or 1 0 (CLR PA.2) 1 (SET PA.2) PA3, PA2 Pad Function PA2=EL1, PA3=EL2 PA2=0, PA3=1
OPTION Register: EL Mode Enable
V
DD
C o n tr o l B it D a ta B u s D CK S Q W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r Q
PH
PA0~PA7 D a ta B it Q D CK S M U X Q
W r ite D a ta R e g is te r
R e a d D a ta R e g is te r S y s te m W a k e -u p
Note: BZ mode and EL mode functions are not shown in this diagram
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HT47C10L
125Hz EL1 2 9/fO (= 4 m s ) 2 9/fO
SC
(= 4 m s )
EL2 E L E N (P A .2 ) 2 EL1 1 /fO EL2 E L E N (P A .2 )
SC 5
SC
/fO
SC
(= 2 5 0 m s )
(= 7 .8 m s )
EL Timing
LCD Display Memory The HT47C10L provides an area of embedded data memory for LCD display. The LCD display memory is designed into 94 bits. This area is located from 40H to 48H of the RAM at Bank 1. Bank pointer (BP; located at 04H of the data memory) is the switch between the general data memory and the LCD display memory. When the BP is set 1 any data written into 40H~48H will effect the LCD display (indirect addressing mode using MP1). When the BP is cleared 0, any data written into
40H 0 1 41H 42H 43H
40H~48H has to access the general-purpose data memory. The LCD display memory can be read and written only by indirect addressing mode using MP1. When data is written into the display data area, it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. To turn the display On or Off, a 1 or a 0 is written to the corresponding bit of the display memory, respectively. The figure illustrates the mapping between the display memory and LCD pattern for the HT47C10L.
44H 45H 46H 47H 48H 0 1
COM
B it
2 2 3 3
SEGMENT
0
1
2
3 4
5
6 7
8
Display Memory (Bank 1)
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LCD Driver Output The output number of the HT47C10L LCD driver is 94 (1/4 duty). The bias type LCD driver is C type (1/2 bias). A capacitor has to be connected between C1 and C2. LCD driver on/off at HALT depends on STANDBY option (Option register bit 5) Low Voltage Detect - LVD The HT47C10L provides a low voltage detector for battery system application. If the LVD is on and the battery voltage is lower than the specified value, the low voltage flag (BLF; bit 4 of ADCR register) is set. The specified value may be set as 1.3V0.05V by changing suitable external RLVD for a same lot. The low voltage detector circuit can be turn On or Off by writing a 1 or a 0 to BON (bit 3 of ADCR register). The BLF is invalid when the BON is cleared as 0.
D u r in g a R e s e t P u ls e : C O M 0 ,C O M 1 ,C O M 2 A ll L C D d r iv e r o u tp u ts VCC* VSS VCC* VSS VCC VDD VSS VCC VDD VSS VCC VDD VSS VCC VDD VSS VCC VDD VSS VCC VDD VSS VCC VDD VSS VCC VDD VSS VCC VDD VSS VCC VDD VSS VCC* VSS VCC* VSS
Set BON=0 after checking the voltage to prevent from DC current consumption of LVD.
BLF ADCR b it 3 BON LVD R LVD
LVD
ADCR
b it 4
N o r m a l O p e r a tio n M o d e : COM0 COM1 COM2 COM3 L C D s e g m e n ts o n C O M 0 ,1 ,2 ,3 s id e s b e in g u n lit O n ly L C D s e g m e n ts o n C O M 0 s id e b e in g lit O n ly L C D s e g m e n ts o n C O M 2 s id e b e in g lit L C D s e g m e n ts o n C O M 1 ,3 s id e s b e in g lit L C D s e g m e n ts o n C O M 0 ,2 ,3 s id e s b e in g lit L C D s e g m e n ts o n C O M 0 ,1 ,2 s id e s b e in g lit L C D O ff M o d e : C O M 0 ,C O M 1 ,C O M 2 ,C O M 3 A ll L C D d r iv e r o u tp u ts
LCD Driver Output (1/4 Duty, 1/2 Bias) Note: VCC is @ 2VDD at normal operation mode. VCC* is @ VDD-0.2V with LCD off or reset.
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Option Register The following shows many kinds of mask options in the HT47C10L. All these options should be defined in order to ensure proper system functioning. Bit No. 0 Label WDTEN Function WDT enable or disable selection (0: enable; 1: disable) Reset State 0
1 2
Buzzer output frequency selection BZFREQ1~BZFREQ0 BZFREQ0, 00: fSYS/22 BZFREQ1 01: fSYS/23 10: fSYS/24 11: fSYS/25 BZMODE To define the PA0 and PA1 output function 0=Normal output 1=Buzzer output. PA0 is BZ output, PA1 is BZ output. To define the PA2 and PA3 output function 0=Normal output 1=EL output. PA2 is EL1 output, PA3 is EL2 output.
01
3
0
4
ELMODE
0
5 6~7
Oscillator/LCD are on or off when CPU HALT STANDBY 0=Oscillator/LCD is off at HALT 1=Oscillator/LCD is on at HALT 3/4 Unused bit, read as 0 OPT1 (26H) Register
0 00
Bit No. 0~7
Label PH
Function PA0~PA7 pull-high option in input mode (0: enable; 1: disable) OPT2 (27H) Register
Reset State 00H
Application Circuits
0 .1 m F VCC C1 C2 P A 0 /B Z P A 1 /B Z 1 .5 V VDD PA4 PA5 PA6 PA7 LVD VSS R C IN 2200pF S ensor VSS H T47C 10L RREF RSEN P A 3 /E L 2 TEST1 TEST2 RES VDD 0 .1 m F 10mF P A 2 /E L 1 1kW SEG 0~8 CO M 0~3 LCD Panel
0 .1 m F
15m H RLS4148 2N5551 EL 100kW 2N5551
100kW 0 .1 m F
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Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
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Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2)
(2)
(3) (1) (4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged.
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Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
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AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr
Operation Affected flag(s)
TO 3/4 CLR [m] Description Operation Affected flag(s) TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation Affected flag(s) TO 0 CLR WDT1 Description PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CLR WDT2 Description
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CPL [m] Description Operation Affected flag(s) TO 3/4
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m]
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
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CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m]
Operation Affected flag(s)
TO 3/4 DAA [m] Description
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s) TO 3/4 DEC [m] Description Operation Affected flag(s) TO 3/4 DECA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1
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HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0
Operation
Affected flag(s) TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
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MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
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RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation Affected flag(s) TO 3/4 RETI Description Operation Affected flag(s) TO 3/4 RL [m] Description Operation Affected flag(s) TO 3/4 RLA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7
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RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7
Affected flag(s) TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7
Operation
Affected flag(s) TO 3/4 RR [m] Description Operation Affected flag(s) TO 3/4 RRA [m] Description Operation Affected flag(s) TO 3/4 RRC [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0
Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
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RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0
Operation
Affected flag(s) TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1)
Operation Affected flag(s)
TO 3/4 SDZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1)
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1)
Operation Affected flag(s)
TO 3/4 SIZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1)
Operation Affected flag(s)
TO 3/4 SNZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
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SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TO 3/4 TABRDC [m] Description Operation Affected flag(s) TO 3/4 TABRDL [m] Description Operation Affected flag(s) TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
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Package Information
44-pin QFP (1010) Outline Dimensions
C D G 23 I 34 22 F A B E 44 12 K 1 11 a J 33 H
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 13 9.90 13 9.90 3/4 3/4 1.90 3/4 3/4 0.73 0.10 0 Nom. 3/4 3/4 3/4 3/4 0.80 0.30 3/4 3/4 0.10 3/4 3/4 3/4 Max. 13.40 10.10 13.40 10.10 3/4 3/4 2.20 2.70 3/4 0.93 0.20 7
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Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2005 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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